Integrating formation of a replacement gate transistor and a non-volatile memory cell using a high-k dielectric

Invention Grant

US08728886B2 Integrating formation of a replacement gate transistor and a non-volatile memory cell using a high-k dielectric 有权

Title translation: 使用高k电介质集成形成替换栅晶体管和非易失性存储单元

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Patent Title: Integrating formation of a replacement gate transistor and a non-volatile memory cell using a high-k dielectric
Patent Title (中): 使用高k电介质集成形成替换栅晶体管和非易失性存储单元
Application No.: US13491771

Application Date: 2012-06-08
Publication No.: US08728886B2

Publication Date: 2014-05-20
Inventor: Mark D. Hall , Mehul D. Shroff
Applicant: Mark D. Hall , Mehul D. Shroff
Applicant Address: US TX Austin
Assignee: Freescale Semiconductor, Inc.
Current Assignee: Freescale Semiconductor, Inc.
Current Assignee Address: US TX Austin
Agent James L. Clingan, Jr.; Joanna G. Chiu
Main IPC: H01L21/00
IPC: H01L21/00

Integrating formation of a replacement gate transistor and a non-volatile memory cell using a high-k dielectric

Abstract:

A first dielectric layer is formed in an NVM region and a logic region. A charge storage layer is formed over the first dielectric layer and is patterned to form a dummy gate in the logic region and a charge storage structure in the NVM region. A second dielectric layer is formed in the NVM and logic regions which surrounds the charge storage structure and dummy gate. The second dielectric layer is removed from the NVM region while protecting the second dielectric layer in the logic region. The dummy gate is removed, resulting in an opening. A third dielectric layer is formed over the charge storage structure and within the opening, and a gate layer is formed over the third dielectric layer and within the opening, wherein the gate layer forms a control gate layer in the NVM region and the gate layer within the opening forms a logic gate.

Abstract(Chinese):

在NVM区域和逻辑区域中形成第一介电层。电荷存储层形成在第一电介质层之上，并被图案化以在逻辑区域中形成伪栅极，并在NVM区域中形成电荷存储结构。在NVM和围绕电荷存储结构和虚拟栅极的逻辑区域中形成第二介质层。从NVM区域去除第二介电层，同时保护逻辑区域中的第二介质层。去除虚拟门，导致开口。在电荷存储结构之上和开口内形成第三电介质层，并且栅极层形成在第三介电层之上和开口内，其中栅极层在NVM区域内形成控制栅极层，在栅极层内形成栅极层开幕式构成逻辑门。

Public/Granted literature

US20130330893A1 INTEGRATING FORMATION OF A REPLACEMENT GATE TRANSISTOR AND A NON-VOLATILE MEMORY CELL USING A HIGH-K DIELECTRIC Public/Granted day:2013-12-12

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备