Invention Grant
- Patent Title: Methods for fabricating an integrated circuit arrangement comprising isolating trenches and a field effect transistor
- Patent Title (中): 用于制造集成电路装置的方法,包括隔离沟槽和场效应晶体管
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Application No.: US12941527Application Date: 2010-11-08
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Publication No.: US08728907B2Publication Date: 2014-05-20
- Inventor: Ronald Kakoschke , Franz Schuler
- Applicant: Ronald Kakoschke , Franz Schuler
- Applicant Address: DE Munich
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Munich
- Priority: DE10321742 20030514
- Main IPC: H01L21/8242
- IPC: H01L21/8242

Abstract:
A memory circuit arrangement and a fabrication method are disclosed. The memory circuit arrangement has a memory cell area. The memory cell area contains memory cell transistors, one column of which are selected using a triple gate area selection transistor. The transistor has gate area that extends into isolating trenches. The isolating trenches isolate the memory cell in different columns of the memory cell array.
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