Invention Grant
US08728924B2 Gate electrodes of a semiconductor device formed by a hard mask and double exposure in combination with a shrink spacer 有权
通过硬掩模形成的半导体器件的栅电极和与收缩间隔物组合的双重曝光

Gate electrodes of a semiconductor device formed by a hard mask and double exposure in combination with a shrink spacer
Abstract:
When forming complex gate electrode structures, a double exposure double etch strategy may be applied, in which the lateral distance in the width direction of the gate electrode structures may be defined prior to forming mask features for defining the gate length. In this case, the width dimension of the mask opening may be adjusted on the basis of a spacer element, which may thus allow providing a reduced dimension on the basis of well-established process techniques.
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