Invention Grant
US08728924B2 Gate electrodes of a semiconductor device formed by a hard mask and double exposure in combination with a shrink spacer
有权
通过硬掩模形成的半导体器件的栅电极和与收缩间隔物组合的双重曝光
- Patent Title: Gate electrodes of a semiconductor device formed by a hard mask and double exposure in combination with a shrink spacer
- Patent Title (中): 通过硬掩模形成的半导体器件的栅电极和与收缩间隔物组合的双重曝光
-
Application No.: US13187795Application Date: 2011-07-21
-
Publication No.: US08728924B2Publication Date: 2014-05-20
- Inventor: Sven Beyer , Andreas Hellmich , Steffen Laufer , Klaus Gebauer
- Applicant: Sven Beyer , Andreas Hellmich , Steffen Laufer , Klaus Gebauer
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Priority: DE102010040066 20100831
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/3213

Abstract:
When forming complex gate electrode structures, a double exposure double etch strategy may be applied, in which the lateral distance in the width direction of the gate electrode structures may be defined prior to forming mask features for defining the gate length. In this case, the width dimension of the mask opening may be adjusted on the basis of a spacer element, which may thus allow providing a reduced dimension on the basis of well-established process techniques.
Public/Granted literature
Information query
IPC分类: