Invention Grant
US08729565B2 Layout design for a high power, GaN-based FET having interdigitated gate, source and drain electrodes
有权
具有交错栅极，源极和漏极的高功率GaN基FET的布局设计
- Patent Title: Layout design for a high power, GaN-based FET having interdigitated gate, source and drain electrodes
- Patent Title (中): 具有交错栅极，源极和漏极的高功率GaN基FET的布局设计
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Application No.: US13965871Application Date: 2013-08-13
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Publication No.: US08729565B2Publication Date: 2014-05-20
- Inventor: LinLin Liu , Milan Pophristic , Boris Peres
- Applicant: Power Integrations, Inc.
- Applicant Address: US CA San Jose
- Assignee: Power Integrations, Inc.
- Current Assignee: Power Integrations, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Mayer & Williams PC
- Agent Stuart H. Mayer
- Main IPC: H01L31/0256
- IPC: H01L31/0256
Abstract:
A FET includes a first and second set of finger arrays that each include a source, gate and drain. A first source pad is electrically coupled to source electrodes in the first set of finger arrays. A second source pad is electrically coupled to the source electrodes in the second set of finger arrays. A common drain pad is electrically coupled to drain electrodes in the first and second set of finger arrays. A first gate pad is electrically coupled to gate electrodes in the first set of finger arrays. A second gate pad is electrically coupled to gate electrodes in the second set of finger arrays. A substrate is also provided on which are disposed the first and second set of finger arrays, the first and second source pads, the common drain pad, and the first and second gate pads.
Public/Granted literature
- US20130328060A1 LAYOUT DESIGN FOR A HIGH POWER, GaN-BASED FET Public/Granted day:2013-12-12
Information query
IPC分类:
