Invention Grant
- Patent Title: Substrate backside peeling control
- Patent Title (中): 底材背面剥离控制
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Application No.: US13722426Application Date: 2012-12-20
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Publication No.: US08729645B2Publication Date: 2014-05-20
- Inventor: Liang-Chen Chi , Wei-Lun Jian , Chia-Ming Tsai , Yu-Min Chang , Chin-Kun Wang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L29/76
- IPC: H01L29/76

Abstract:
Structures and methods for reducing backside polysilicon peeling are disclosed. A structure includes a substrate having a first side and a second opposite side, a first dielectric layer on the second side of the substrate extending in a direction from an edge of the substrate towards a center of the substrate, a high-k layer on the first dielectric layer, and a polysilicon layer on the high-k layer. The first dielectric layer has a first innermost sidewall relative to the center of the substrate, and the high-k layer has a second innermost sidewall relative to the center of the substrate. The second innermost sidewall is within 2 millimeters from the first innermost sidewall in a direction parallel to the second side. The polysilicon layer extends towards the center of the substrate further than the first innermost sidewall.
Public/Granted literature
- US20140061822A1 SUBSTRATE BACKSIDE PEELING CONTROL Public/Granted day:2014-03-06
Information query
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