Invention Grant
- Patent Title: Method of manufacturing semiconductor device, semiconductor device and multilayer wafer structure
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Application No.: US12872966Application Date: 2010-08-31
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Publication No.: US08729698B2Publication Date: 2014-05-20
- Inventor: Tadahiro Morifuji , Haruo Shimamoto , Chuichi Miyazaki , Toshihide Uematsu , Yoshiyuki Abe
- Applicant: Tadahiro Morifuji , Haruo Shimamoto , Chuichi Miyazaki , Toshihide Uematsu , Yoshiyuki Abe
- Applicant Address: JP Kyoto JP Kanagawa
- Assignee: Rohm Co., Ltd.,Renesas Electronics Corporation
- Current Assignee: Rohm Co., Ltd.,Renesas Electronics Corporation
- Current Assignee Address: JP Kyoto JP Kanagawa
- Agency: Rabin & Berdo, P.C.
- Priority: JP2009-223266 20090928
- Main IPC: H01L23/488
- IPC: H01L23/488

Abstract:
Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line.
Public/Granted literature
- US20110074017A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND MULTILAYER WAFER STRUCTURE Public/Granted day:2011-03-31
Information query
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