Invention Grant
- Patent Title: Current source with low power consumption and reduced on-chip area occupancy
- Patent Title (中): 电流源具有低功耗和片上占用面积
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Application No.: US13171491Application Date: 2011-06-29
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Publication No.: US08729883B2Publication Date: 2014-05-20
- Inventor: Yanyi L. Wong , Agustinus Sutandi
- Applicant: Yanyi L. Wong , Agustinus Sutandi
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Baker Botts L.L.P.
- Main IPC: G05F3/04
- IPC: G05F3/04

Abstract:
A current source with low power consumption and reduced on-chip area occupancy. The current source for providing a constant current to a load includes a first circuit that generates a reference current. The first circuit includes a first plurality of interconnected transistors. The current source also includes a characteristic resistor, coupled to the first circuit, that determines value of the reference current. The current source further includes a second circuit and a third circuit. The second circuit, coupled to the first circuit and to the load, generates an output current that is identical to the reference current. The second circuit includes a second plurality of interconnected transistors. The third circuit, coupled to the first circuit, drives a multiple of the reference current into the characteristic resistor. The third circuit includes a third plurality of interconnected transistors.
Public/Granted literature
- US20130002228A1 CURRENT SOURCE WITH LOW POWER CONSUMPTION AND REDUCED ON-CHIP AREA OCCUPANCY Public/Granted day:2013-01-03
Information query
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