Invention Grant
US08730215B2 Data latch circuit, driving method of the data latch circuit, and display device
有权
数据锁存电路,数据锁存电路的驱动方法及显示装置
- Patent Title: Data latch circuit, driving method of the data latch circuit, and display device
- Patent Title (中): 数据锁存电路,数据锁存电路的驱动方法及显示装置
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Application No.: US13069431Application Date: 2011-03-23
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Publication No.: US08730215B2Publication Date: 2014-05-20
- Inventor: Mitsuaki Osame , Tatsuo Ueno
- Applicant: Mitsuaki Osame , Tatsuo Ueno
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Fish & Richardson P.C.
- Priority: JP2005-133654 20050428
- Main IPC: H03K3/00
- IPC: H03K3/00 ; H03K19/096 ; H03K19/20 ; G06F3/038 ; G09G5/00 ; G09G3/36

Abstract:
The present invention provides a data latch circuit which can operate stably with a low-amplitude signal, which consumes less electric power, and which is resistant against the variation in TFTs. When an analog switch is turned on, a data signal is inputted to a gate electrode of an n-channel TFT and, at this time, VDD is supplied to an input terminal of an inverter. When the analog switch in turned off, the n-channel TFT is turned on or off depending on a level of the data signal. When the data signal is at an H level, the n-channel TFT is turned on and VSS is supplied to the input terminal of the inverter. When the data signal is at an L level, VDD is supplied to an input terminal of the inverter. Therefore, only VDD and VSS levels are applied to the input terminal of the inverter.
Public/Granted literature
- US20110169548A1 DATA LATCH CIRCUIT, DRIVING METHOD OF THE DATA LATCH CIRCUIT, AND DISPLAY DEVICE Public/Granted day:2011-07-14
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