A method of operating a memory circuit compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The method includes selecting a word line (708) connected to a row of memory cells in response to a plurality of row address signals and selecting a plurality of columns (706,710) of memory cells in response to a plurality of column address signals. A first part (714) of the plurality of columns is selected in response to a first voltage applied to the selected word line. A second part (716) of the plurality of columns is selected in response to a second voltage applied to the selected word line.