Invention Grant
US08730739B2 Semiconductor device for accelerating erase verification process and method therefor 有权
用于加速擦除验证过程的半导体器件及其方法

Semiconductor device for accelerating erase verification process and method therefor
Abstract:
A semiconductor device and a method for accelerating erase verification process thereof are introduced, in which a correction unit of erase verification is connected between broken bit lines of the semiconductor device and a page buffer. Grounding switches in the correction unit of erase verification are allowed to connect the broken bit lines to ground during an erase verification process by means of a specific circuit arrangement with respect to the broken lines. Thereby, the earth voltage is received, and further, that the broken bit lines pass the erase verification is identified by the page buffer, further saving time consumed in repeated verifications in the conventional technology significantly.
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