Invention Grant
- Patent Title: Memory system
- Patent Title (中): 内存系统
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Application No.: US13602626Application Date: 2012-09-04
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Publication No.: US08730757B2Publication Date: 2014-05-20
- Inventor: Yuui Shimizu
- Applicant: Yuui Shimizu
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2012-070160 20120326
- Main IPC: G11C8/00
- IPC: G11C8/00

Abstract:
According to one embodiment, a memory system includes a first semiconductor memory and a controller. The first semiconductor memory receives a first clock, and outputs, in accordance with the first clock, a second clock and a data signal in synchronization with the second clock. The controller includes a detection circuit which detects a shift of a duty ratio of the second clock which is output from the first semiconductor memory. The controller also includes an adjustment circuit which adjusts a duty ratio of the first clock based on the shift detected by the detection circuit.
Public/Granted literature
- US20130250693A1 MEMORY SYSTEM Public/Granted day:2013-09-26
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