Invention Grant
- Patent Title: Parallel closed-loop DFE filter architecture
- Patent Title (中): 并联闭环DFE滤波器架构
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Application No.: US13450265Application Date: 2012-04-18
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Publication No.: US08731041B2Publication Date: 2014-05-20
- Inventor: Anton Pelteshki , John Hogeboom
- Applicant: Anton Pelteshki , John Hogeboom
- Applicant Address: CA Ottawa
- Assignee: STMicroelectronics (Canada) Inc.
- Current Assignee: STMicroelectronics (Canada) Inc.
- Current Assignee Address: CA Ottawa
- Agency: Hogan Lovells US LLP
- Main IPC: H03H7/30
- IPC: H03H7/30
Abstract:
A DFE filter includes an input, a first filter loop coupled to the input for providing an odd bit-stream, and a second filter loop coupled to the input for providing an even bit-stream, wherein the first and second filter loops are identical and interleaved.
Public/Granted literature
- US20120269255A1 Parallel Closed-Loop DFE Filter Architecture Public/Granted day:2012-10-25
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