Invention Grant
- Patent Title: Method and processor unit for implementing a characteristic-2-multiplication
- Patent Title (中): 用于实现特征2乘法的方法和处理器单元
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Application No.: US13055218Application Date: 2009-05-22
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Publication No.: US08732227B2Publication Date: 2014-05-20
- Inventor: Jean Georgiades , Bernd Meyer
- Applicant: Jean Georgiades , Bernd Meyer
- Applicant Address: DE Munich
- Assignee: Siemens Aktiengesellschaft
- Current Assignee: Siemens Aktiengesellschaft
- Current Assignee Address: DE Munich
- Agency: King & Spalding L.L.P.
- Priority: DE102008033962 20080721
- International Application: PCT/EP2009/056228 WO 20090522
- International Announcement: WO2010/009917 WO 20100128
- Main IPC: G06F7/52
- IPC: G06F7/52

Abstract:
The method for implementing a characteristic-2-multiplication of at least two input bit strings each having a number N of bits by means of a processor unit suitable for carrying out an integer multiplication, having the following steps: a) generating at least one sequence of a number K of zero bits, using Kε{1, . . . , N}, by means of a first transformation of the respective input bit string to at least one predetermined position in the respective input bit string for generating at least one first intermediate bit string; b) linking the at least two first intermediate bit strings by means of the integer multiplication of the processor unit for generating at least one second intermediate bit string; and c) transforming the at least one second intermediate bit string by means of a second transformation for generating a result bit string.
Public/Granted literature
- US20110131395A1 METHOD AND PROCESSOR UNIT FOR IMPLEMENTING A CHARACTERISTIC-2-MULTIPLICATION Public/Granted day:2011-06-02
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