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US08732227B2 Method and processor unit for implementing a characteristic-2-multiplication 有权
用于实现特征2乘法的方法和处理器单元

Method and processor unit for implementing a characteristic-2-multiplication
Abstract:
The method for implementing a characteristic-2-multiplication of at least two input bit strings each having a number N of bits by means of a processor unit suitable for carrying out an integer multiplication, having the following steps: a) generating at least one sequence of a number K of zero bits, using Kε{1, . . . , N}, by means of a first transformation of the respective input bit string to at least one predetermined position in the respective input bit string for generating at least one first intermediate bit string; b) linking the at least two first intermediate bit strings by means of the integer multiplication of the processor unit for generating at least one second intermediate bit string; and c) transforming the at least one second intermediate bit string by means of a second transformation for generating a result bit string.
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