A device includes a processor, unified DMA (‘Direct Memory Access’) storage, and a number of DMA engines. The processor may be operatively coupled to the unified DMA storage and a main memory. The DMA engines may be configured to access the unified DMA storage and provide DMA transmissions between the main memory and a corresponding component. The processor may be configured to: determine a size of a corresponding DMA buffer to be allocated for each DMA engine; allocate, for each DMA engine, the corresponding DMA buffer of the determined size in the unified DMA storage; and execute DMA transmission using the DMA engines and the corresponding DMA buffers.