In a semiconductor LSI that sequentially performs predetermined processing on data input successively, a host CPU, a plurality of sequencers, and a data engine are connected in a hierarchical manner with the host CPU at top and the data engine at bottom. Each sequencer includes a memory that stores a parameter for execution of the sequencer, a memory controller, a loop counter, a sequence controller, and an interface unit that handles transmission and reception of signals with an external unit of the sequencer. The interface units of the plurality of sequencers have the same specifications.