Invention Grant
- Patent Title: Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language
- Patent Title (中): 使用系统虚拟硬件描述语言实现模拟行为建模和IP集成的方法，系统和制造
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Application No.: US13831958Application Date: 2013-03-15
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Publication No.: US08732630B1Publication Date: 2014-05-20
- Inventor: Abhijeet S. Kolpekwar , Aaron M. Spratt , William S. Cranston , Chandrashekar L. Chetput
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
Some embodiments provide support for real number modeling in SystemVerilog by defining built-in nettypes with real data type and resolution functions natively in SystemVerilog and allow a simple path for porting Verilog-AMS wreal modeling to SystemVerilog modeling. Some embodiments provide support for incompatible nettypes and for net coercion in SystemVerilog. Some embodiments provide support for SystemVerilog reals net connecting to electrical nets and support for SystemVerilog real signals connecting to Verilog-AMS wreal signals. Some embodiments combine the strengths of Verilog-AMS and SystemVerilog languages to build a solution for value conversion between incompatible nets and an effective way to configure, simulate, or verify mixed-signal designs that are written in SystemVerilog language.
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