Invention Grant
US08732637B2 Formal verification of bit-serial division and bit-serial square-root circuit designs
有权
位串行分频和位串行平方根电路设计的正式验证
- Patent Title: Formal verification of bit-serial division and bit-serial square-root circuit designs
- Patent Title (中): 位串行分频和位串行平方根电路设计的正式验证
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Application No.: US13561895Application Date: 2012-07-30
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Publication No.: US08732637B2Publication Date: 2014-05-20
- Inventor: Himanshu Jain , Carl P. Pixley
- Applicant: Himanshu Jain , Carl P. Pixley
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Park, Vaughan, Fleming & Dowler LLP
- Agent Laxman Sahasrabuddhe
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455 ; G01R31/28 ; G06F11/00 ; G06F7/02

Abstract:
Methods and apparatuses are described for formally verifying a bit-serial division circuit design or a bit-serial square-root circuit design. Some embodiments formally verify a bit-serial division circuit design using a set of properties that can be efficiently proven using a bit-level solver. In some embodiments, the set of properties that are used for verifying a bit-serial division circuit design does not include any terms that multiply a w-bit partial quotient with the divisor. Some embodiments formally verify a bit-serial square-root circuit design using a set of properties that can be efficiently proven using a bit-level solver. In some embodiments, the set of properties that are used for verifying a bit-serial square-root circuit design does not include any terms that compute a square of a w-bit partial square-root.
Public/Granted literature
- US20140033150A1 FORMAL VERIFICATION OF BIT-SERIAL DIVISION AND BIT-SERIAL SQUARE-ROOT CIRCUIT DESIGNS Public/Granted day:2014-01-30
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