Invention Grant
- Patent Title: Logical design flow with structural compatability verification
- Patent Title (中): 具有结构兼容性验证的逻辑设计流程
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Application No.: US12422959Application Date: 2009-04-13
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Publication No.: US08732651B1Publication Date: 2014-05-20
- Inventor: Taranjit Singh Kukal , Nikhil Gupta , Steve Durrill , Vikrant Khanna , Dingru Xiao
- Applicant: Taranjit Singh Kukal , Nikhil Gupta , Steve Durrill , Vikrant Khanna , Dingru Xiao
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Rosenberg, Klein & Lee
- Main IPC: G06F15/04
- IPC: G06F15/04 ; G06F17/50

Abstract:
A design system provides data structures to store parameters of physical structures that can be viewed and modified in a front-end process through a logical design interface. In this way, system behavior defined by component structure can be evaluated and modified through a schematic representation of the data, regardless of a state of data representing the physical layout of interconnected physical structures. In electric circuit applications, for example, high frequency circuits can be incrementally designed and evaluated through structural parameters defined in a schematic diagram data abstraction without modifying and evaluating a layout data abstraction of the circuit directly.
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