Invention Grant
- Patent Title: Synthesis of concurrent schedulers for multicore architectures
- Patent Title (中): 多核架构的并发调度程序的综合
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Application No.: US13154080Application Date: 2011-06-06
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Publication No.: US08732712B2Publication Date: 2014-05-20
- Inventor: Keshav Kumar Pingali , Donald Do Nguyen
- Applicant: Keshav Kumar Pingali , Donald Do Nguyen
- Applicant Address: US TX Austin
- Assignee: Board Of Regents Of the University of Texas System
- Current Assignee: Board Of Regents Of the University of Texas System
- Current Assignee Address: US TX Austin
- Agency: Ballard Spahr LLP
- Main IPC: G06F9/46
- IPC: G06F9/46

Abstract:
Systems and methods provide a high-level language for generation of a scheduling specification based on a scheduling policy, and synthesis of scheduler based on the scheduling specification. The systems and methods can permit the use of more sophisticated scheduling strategies than those afforded by conventional systems, without requiring the programmer to write explicitly parallel code. In certain embodiments, synthesis of the scheduler includes implementation of at least one rule related to the scheduling specification through definition of one or more workset objects that are concurrent, a workset object of the one or more workset objects having an addition method, a first poll method, and a second poll method. Such poll methods extend the operability of sequential poll methods. The one or more worksets satisfy a condition for correctness that is less stringent than conventional conditions for correctness.
Public/Granted literature
- US20110302584A1 SYNTHESIS OF CONCURRENT SCHEDULERS FOR MULTICORE ARCHITECTURES Public/Granted day:2011-12-08
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