Invention Grant
US08735221B2 Stacked package, method of fabricating stacked package, and method of mounting stacked package fabricated by the method
有权
堆叠封装,堆叠封装的制造方法以及通过该方法制造的堆叠封装的安装方法
- Patent Title: Stacked package, method of fabricating stacked package, and method of mounting stacked package fabricated by the method
- Patent Title (中): 堆叠封装,堆叠封装的制造方法以及通过该方法制造的堆叠封装的安装方法
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Application No.: US13242183Application Date: 2011-09-23
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Publication No.: US08735221B2Publication Date: 2014-05-27
- Inventor: Jae-Wook Yoo , Sun-Kyoung Seo
- Applicant: Jae-Wook Yoo , Sun-Kyoung Seo
- Applicant Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Consulting, PLLC
- Priority: KR10-2010-0119762 20101129
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
Provided are a stacked package, method of fabricating a stacked package, and method of mounting a stacked package. A method includes providing an upper semiconductor package including an upper package substrate, upper semiconductor chips formed on a top surface of the upper package substrate, and first solders formed on a bottom surface of the upper package substrate and having a first melting temperature, providing a lower semiconductor package including a lower package substrate, lower semiconductor chips formed on a top surface of the lower package substrate, and solder paste nodes formed on the top surface of the lower package substrate and having a second melting temperature lower than the first melting temperature, and forming inter-package bonding units by attaching respective first solders and solder paste nodes to each other by performing annealing at a temperature higher than the second melting temperature and lower than the first melting temperature.
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Information query
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