Invention Grant
- Patent Title: Manufacture method of a high voltage MOS semiconductor device
- Patent Title (中): 高压MOS半导体器件的制造方法
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Application No.: US13779163Application Date: 2013-02-27
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Publication No.: US08735254B2Publication Date: 2014-05-27
- Inventor: Masashi Shima , Kazukiyo Joshin , Toshihide Suzuki
- Applicant: Fujitsu Semiconductor Limited
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A semiconductor device has: a low concentration drain region creeping under a gate electrode of a MIS type transistor; a high concentration drain region having an impurity concentration higher than the low concentration drain region and formed in the low concentration drain region spaced apart from the gate electrode; and an opposite conductivity type region of a conductivity type opposite to the drain region formed in the low concentration drain region on a surface area between the high concentration drain region and the gate electrode, the opposite conductivity type region and low concentration drain region forming a pn junction.
Public/Granted literature
- US20130171791A1 SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD Public/Granted day:2013-07-04
Information query
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