Invention Grant
- Patent Title: Via-configurable high-performance logic block architecture
- Patent Title (中): 通过可配置的高性能逻辑块架构
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Application No.: US13271679Application Date: 2011-10-12
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Publication No.: US08735857B2Publication Date: 2014-05-27
- Inventor: Alexander Andreev , Sergey Gribok , Ranko Scepanovic
- Applicant: Alexander Andreev , Sergey Gribok , Ranko Scepanovic
- Applicant Address: US CA Santa Clara
- Assignee: eASIC Corporation
- Current Assignee: eASIC Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Novak Druce Connolly Bove + Quigg LLP
- Main IPC: H01L27/08
- IPC: H01L27/08 ; H01L47/00
Abstract:
A via-configurable circuit block may contain chains of p-type and n-type transistors that may or may not be interconnected by means of configurable vias. Configurable vias may also be used to connect various transistor terminals to a ground line, a power line and/or to various terminals that may provide connections outside of the circuit block.
Public/Granted literature
- US20120161093A1 Via-Configurable High-Performance Logic Block Architecture Public/Granted day:2012-06-28
Information query
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