Invention Grant
US08735944B2 Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with serially connected transistors
有权
集成电路包括交叉耦合晶体管,其栅极电极形成在具有串联连接的晶体管的栅极级特征布局通道内
- Patent Title: Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with serially connected transistors
- Patent Title (中): 集成电路包括交叉耦合晶体管,其栅极电极形成在具有串联连接的晶体管的栅极级特征布局通道内
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Application No.: US12754078Application Date: 2010-04-05
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Publication No.: US08735944B2Publication Date: 2014-05-27
- Inventor: Scott T. Becker , Jim Mali , Carole Lambert
- Applicant: Scott T. Becker , Jim Mali , Carole Lambert
- Applicant Address: US CA Los Gatos
- Assignee: Tela Innovations, Inc.
- Current Assignee: Tela Innovations, Inc.
- Current Assignee Address: US CA Los Gatos
- Agency: Martine Penilla Group, LLP
- Main IPC: H01L27/10
- IPC: H01L27/10 ; H01L27/02 ; H01L27/088 ; H01L27/092

Abstract:
A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features that are each defined within any one gate level channel. At least a portion of the first p-type diffusion region and at least a portion of the second p-type diffusion region are formed over a first common line of extent that extends perpendicular to the first parallel direction. Also, at least a portion of the first n-type diffusion region and at least a portion of the second n-type diffusion region are formed over a second common line of extent that extends perpendicular to the first parallel direction.
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Information query
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