Invention Grant
- Patent Title: Vertical MOSFET transistor with a vertical capacitor region
- Patent Title (中): 具有垂直电容器区域的垂直MOSFET晶体管
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Application No.: US13549684Application Date: 2012-07-16
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Publication No.: US08735957B2Publication Date: 2014-05-27
- Inventor: Phil Rutter
- Applicant: Phil Rutter
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Priority: EP11176349 20110802
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L29/76 ; H01L29/94 ; H01L31/119

Abstract:
Consistent with an example embodiment, there is a package that includes a first voltage terminal, and a second voltage terminal, a first die including a first MOSFET having a drain region electrically connected to the first voltage terminal and further having a source region, A second die is adjacent to the first die, the second die includes a second MOSFET having a drain region electrically connected to the source region of the first MOSFET and having a source region electrically connected to the second voltage terminal. The semiconductor package further includes a vertical capacitor having a first plate electrically connected to the drain region of the first MOSFET and a second plate electrically connected to the source region of the second MOSFET and the second plate is electrically insulated from the first plate by a dielectric material. The capacitor is integrated on the first die or the second die.
Public/Granted literature
- US20130181272A1 IC DIE, SEMICONDUCTOR PACKAGE, PRINTED CIRCUIT BOARD AND IC DIE MANUFACTURING METHOD Public/Granted day:2013-07-18
Information query
IPC分类: