Invention Grant
- Patent Title: Frequency divider and phase locked loop including the same
- Patent Title (中): 分频器和锁相环包括相同的
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Application No.: US13535424Application Date: 2012-06-28
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Publication No.: US08736317B2Publication Date: 2014-05-27
- Inventor: Hwan-Seok Yeo , Ji-Hyun Kim
- Applicant: Hwan-Seok Yeo , Ji-Hyun Kim
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel Sibley & Sajovec, P.A.
- Priority: KR10-2011-0063687 20110629
- Main IPC: H03K23/00
- IPC: H03K23/00 ; H03K21/00

Abstract:
A frequency includes a first edge detection unit configured to generate a first count signal responsive to detecting first edges of an input signal and a second edge detection unit configured to generate a second count signal responsive to detecting the first edges of the input signal in a first operation mode and to generate the second count signal responsive to detecting second edges of the input signal in a second operation mode. One of the first and second edges is a rising edge and the other of the first and second edges is a falling edge. A pulse triggered buffer unit generates an output signal responsive to the first and second count signals. The output signal is divided by a target division ratio with respect to the input signal that is an odd number division ratio in one mode and an even number division ratio in the other mode.
Public/Granted literature
- US20130002319A1 Frequency Divider and Phase Locked Loop Including the Same Public/Granted day:2013-01-03
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