Invention Grant
US08736317B2 Frequency divider and phase locked loop including the same 有权
分频器和锁相环包括相同的

Frequency divider and phase locked loop including the same
Abstract:
A frequency includes a first edge detection unit configured to generate a first count signal responsive to detecting first edges of an input signal and a second edge detection unit configured to generate a second count signal responsive to detecting the first edges of the input signal in a first operation mode and to generate the second count signal responsive to detecting second edges of the input signal in a second operation mode. One of the first and second edges is a rising edge and the other of the first and second edges is a falling edge. A pulse triggered buffer unit generates an output signal responsive to the first and second count signals. The output signal is divided by a target division ratio with respect to the input signal that is an odd number division ratio in one mode and an even number division ratio in the other mode.
Public/Granted literature
Information query
Patent Agency Ranking
0/0