Invention Grant
US08736328B2 Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces
有权
低功耗，抖动和延迟时钟，具有用于封装输入/输出接口的公共参考时钟信号
- Patent Title: Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces
- Patent Title (中): 低功耗，抖动和延迟时钟，具有用于封装输入/输出接口的公共参考时钟信号
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Application No.: US13994808Application Date: 2011-12-22
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Publication No.: US08736328B2Publication Date: 2014-05-27
- Inventor: Nasser A. Kurd , Thomas P. Thomas
- Applicant: Nasser A. Kurd , Thomas P. Thomas
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- International Application: PCT/US2011/066990 WO 20111222
- International Announcement: WO2013/095549 WO 20130627
- Main IPC: H03L7/06
- IPC: H03L7/06
Abstract:
Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces. A filter phase locked loop circuit in a master device on a first die provides a clock signal having a frequency of 2F. A local phase locked loop circuit in the master device on the first die is coupled with the filter phase locked loop to provide a clock signal to functional components of the master device through a local clock divider circuit to provide a clock signal of F to the functional components. A remote phase locked loop circuit in a slave device on a second die is coupled with the filter phase locked loop to provide a clock signal to one or more functional components of the slave device through a local clock divider circuit to provide a clock signal of F to the functional components.
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