A calibration control circuit is provided for calibrating a stage in a pipeline analog-to-digital converter (ADC). The stage includes an analog-to-digital subconverter (ADSC) and a multiplying digital-to-analog converter (MDAC). The calibration control circuit includes circuitry coupled to comparators in the ADSC to force the comparators to output a predetermined digital output signal set by a calibration control signal when the ADC is in a calibration mode to thereby control reference switches in an analog multiplexer (AMUX) to selectively apply reference voltages to capacitors in the MDAC to obtain a predetermined stage residue signal.