A multi-die memory device includes a first die of a first type and configured to electrically interface with an external processor via a first synchronous interface operating at a first clock rate, and at least one second die of a second type and configured for data storage. Each second die transacts data with the first die via a second synchronous interface operating at a second clock rate, where the first clock rate is an integer multiple of the second clock rate, and where a timing reference associated with the second synchronous interface is transmitted by the first die to the second die.