A hardware interrupt processing circuit converts selected hardware interrupts to an interrupt vector having bits corresponding to the selected hardware interrupts. The hardware interrupt processing circuit includes circuit assemblies that correspond to the selected hardware interrupts. Each circuit assembly includes a detector circuit and a persistent capture circuit. The detector circuit is to output a pulse responsive to the corresponding selected hardware interrupt being asserted. The persistent capture circuit is triggered by the persistent capture circuit to output a corresponding bit of the interrupt vector until a ready signal has been asserted.