Invention Grant
US08739010B2 Memory array with redundant bits and memory element voting circuits
有权
具有冗余位和存储元件投票电路的存储器阵列
- Patent Title: Memory array with redundant bits and memory element voting circuits
- Patent Title (中): 具有冗余位和存储元件投票电路的存储器阵列
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Application No.: US12950944Application Date: 2010-11-19
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Publication No.: US08739010B2Publication Date: 2014-05-27
- Inventor: Yanzhong Xu
- Applicant: Yanzhong Xu
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Treyz Law Group
- Agent G. Victor Treyz; David C. Kellogg
- Main IPC: G06F11/08
- IPC: G06F11/08

Abstract:
An integrated circuit may have an array of memory elements. Each memory element may have multiple memory cells. Each memory element may have a voting circuit that receives signals from the memory cells in that memory element. The voting circuit can produce an output based on the signals. The signals stored by the memory cells of each memory element may be redundant so that the voting circuit can produce an accurate output even in the event that a radiation strike causes some of the memory cells to flip their states to erroneous values. The memory elements may be based on memory cells such as static random-access memory cells and thyristor-based cells.
Public/Granted literature
- US20120131424A1 MEMORY ARRAY WITH REDUNDANT BITS AND MEMORY ELEMENT VOTING CIRCUITS Public/Granted day:2012-05-24
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