Invention Grant
US08739141B2 Parallelizing non-countable loops with hardware transactional memory
有权
将不可计数的循环与硬件事务内存并行化
- Patent Title: Parallelizing non-countable loops with hardware transactional memory
- Patent Title (中): 将不可计数的循环与硬件事务内存并行化
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Application No.: US12123176Application Date: 2008-05-19
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Publication No.: US08739141B2Publication Date: 2014-05-27
- Inventor: Yonghong Song , Spiros Kalogeropulos , Partha P. Tirumalai
- Applicant: Yonghong Song , Spiros Kalogeropulos , Partha P. Tirumalai
- Applicant Address: US CA Redwood Shores
- Assignee: Oracle America, Inc.
- Current Assignee: Oracle America, Inc.
- Current Assignee Address: US CA Redwood Shores
- Agency: Meyertons, Hood, Kivlin, Kowart & Goetzel, P.C.
- Agent Rory D. Rankin
- Main IPC: G06F9/45
- IPC: G06F9/45

Abstract:
A system and method for speculatively parallelizing non-countable loops in a multi-threaded application. A multi-core processor receives instructions for a multi-threaded application. The application may contain non-countable loops. Non-countable loops have an iteration count value that cannot be determined prior to the execution of the non-countable loop, a loop index value that cannot be non-speculatively determined prior to the execution of an iteration of the non-countable loop, and control that is not transferred out of the loop body by a code line in the loop body. The compiler replaces the non-countable loop with a parallelized loop pattern that uses outlined function calls defined in a parallelization library (PL) in order to speculatively execute iterations of the parallelized loop. The parallelized loop pattern is configured to squash and re-execute any speculative thread of the parallelized loop pattern that is signaled to have a transaction failure.
Public/Granted literature
- US20090288075A1 PARALLELIZING NON-COUNTABLE LOOPS WITH HARDWARE TRANSACTIONAL MEMORY Public/Granted day:2009-11-19
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