Invention Grant
- Patent Title: Method of forming a gate pattern and a semiconductor device
- Patent Title (中): 形成栅极图案和半导体器件的方法
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Application No.: US13240637Application Date: 2011-09-22
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Publication No.: US08741744B2Publication Date: 2014-06-03
- Inventor: Qiyang He , Yiying Zhang
- Applicant: Qiyang He , Yiying Zhang
- Applicant Address: CN Shanghai
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee Address: CN Shanghai
- Agency: Koppel, Patrick, Heybl & Philpott
- Agent Michael J. Ram
- Priority: CN201110064415 20110317
- Main IPC: H01L21/20
- IPC: H01L21/20 ; H01L21/36 ; H01L21/3205 ; H01L21/4763

Abstract:
This disclosure is directed to a method of forming a gate pattern and a semiconductor device. The method comprises: providing a plurality of stacked structures which are parallel to each other and extend continuously in a first direction, and which are composed of a gate material bar and an etching barrier bar thereon; leaving second resist regions between gaps to be formed adjacent to each other across gate bars by a second photolithography process; selectively removing the etching barrier bars by a second etching process; forming a third resist layer having a plurality of openings parallel to each other and extending continuously in a second direction substantially perpendicular to the first direction by a third photolithography process; and forming the gate pattern by a third etching process. The method is capable of having a larger photolithography process window and better controlling the shape and size of a gate pattern.
Public/Granted literature
- US20120235243A1 METHOD OF FORMING A GATE PATTERN AND A SEMICONDUCTOR DEVICE Public/Granted day:2012-09-20
Information query
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