Invention Grant
- Patent Title: Fabricating method of non-volatile memory
- Patent Title (中): 非易失性存储器的制作方法
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Application No.: US13845106Application Date: 2013-03-18
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Publication No.: US08741754B2Publication Date: 2014-06-03
- Inventor: Ya-Jui Lee , Ying-Chia Lin
- Applicant: Powerchip Technology Corporation
- Applicant Address: TW Hsinchu
- Assignee: Powerchip Technology Corporation
- Current Assignee: Powerchip Technology Corporation
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Priority: TW99145267A 20101222
- Main IPC: H01L21/8247
- IPC: H01L21/8247 ; H01L29/792

Abstract:
A fabricating method of a non-volatile memory is provided. A tunneling dielectric layer and a first conductive layer are sequentially formed on a substrate. Isolation structures are formed in the first conductive layer, the tunneling dielectric layer and the substrate. The first conductive layer is patterned to form protruding portions. A portion of the isolation structures is removed, so that a top surface of each isolation structure is disposed between a top surface of the first conductive layer and a surface of the substrate. An inter-gate dielectric layer is formed on the substrate. A second conductive layer is formed on the inter-gate dielectric layer. The second conductive layer is patterned to form control gates, and the first conductive layer is patterned to form floating gates. The protruding portion of each floating gate is fully covered and surrounded by the control gate in any direction.
Public/Granted literature
- US20130217218A1 FABRICATING METHOD OF NON-VOLATILE MEMORY Public/Granted day:2013-08-22
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