Invention Grant
- Patent Title: Through silicon via dies and packages
- Patent Title (中): 通过芯片通过芯片和封装
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Application No.: US14058310Application Date: 2013-10-21
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Publication No.: US08741762B2Publication Date: 2014-06-03
- Inventor: Hao Liu , Yi Sheng Anthony Sun , Ravi Kanth Kolan , Chin Hock Toh
- Applicant: United Test and Assembly Center Ltd.
- Applicant Address: SG Singapore
- Assignee: United Test and Assembly Center Ltd.
- Current Assignee: United Test and Assembly Center Ltd.
- Current Assignee Address: SG Singapore
- Agency: Horizon IP Pte. Ltd.
- Main IPC: H01L21/768
- IPC: H01L21/768

Abstract:
A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings.
Public/Granted literature
- US20140045301A1 THROUGH SILICON VIA DIES AND PACKAGES Public/Granted day:2014-02-13
Information query
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