Invention Grant
- Patent Title: Methods of forming semiconductor constructions
- Patent Title (中): 形成半导体结构的方法
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Application No.: US13529006Application Date: 2012-06-21
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Publication No.: US08741781B2Publication Date: 2014-06-03
- Inventor: Justin B. Dorhout , Ranjan Khurana , David Swindler , Jianming Zhou
- Applicant: Justin B. Dorhout , Ranjan Khurana , David Swindler , Jianming Zhou
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L21/461
- IPC: H01L21/461

Abstract:
Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base.
Public/Granted literature
- US20130341795A1 Methods of Forming Semiconductor Constructions Public/Granted day:2013-12-26
Information query
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