Invention Grant
- Patent Title: Three-dimensional semiconductor device including a mold structure providing gap regions and an interconnection structure including a plurality of interconnection patterns formed in the gap regions
- Patent Title (中): 三维半导体器件包括提供间隙区域的模具结构和包括形成在间隙区域中的多个互连图案的互连结构
-
Application No.: US12953748Application Date: 2010-11-24
-
Publication No.: US08742466B2Publication Date: 2014-06-03
- Inventor: Jae-Joo Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Woojin Cho
- Applicant: Jae-Joo Shim , Hansoo Kim , Wonseok Cho , Jaehoon Jang , Woojin Cho
- Applicant Address: KR Suwon-Si, Gyeonggi-Do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-Si, Gyeonggi-Do
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2009-0126854 20091218
- Main IPC: H01L23/52
- IPC: H01L23/52

Abstract:
Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.
Public/Granted literature
- US20110147801A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Public/Granted day:2011-06-23
Information query
IPC分类: