Invention Grant
US08742512B2 Border between semiconductor transistors with different gate structures 有权
具有不同门结构的半导体晶体管之间的边界

  • Patent Title: Border between semiconductor transistors with different gate structures
  • Patent Title (中): 具有不同门结构的半导体晶体管之间的边界
  • Application No.: US13609866
    Application Date: 2012-09-11
  • Publication No.: US08742512B2
    Publication Date: 2014-06-03
  • Inventor: Takeshi Kishida
  • Applicant: Takeshi Kishida
  • Agency: Young & Thompson
  • Priority: JP2011-207329 20110922
  • Main IPC: H01L21/70
  • IPC: H01L21/70
Border between semiconductor transistors with different gate structures
Abstract:
A semiconductor device according to the invention includes: a first region on a semiconductor substrate, in which a first transistor is formed, the first transistor including first gate insulating film 4 containing a high dielectric constant material and first metal gate electrode 5 formed on first gate insulating film 4; a second region adjacent to the first region on the semiconductor substrate, in which a second transistor is formed, the second transistor including second gate insulating film 4 and second metal gate electrode 12 formed on the second gate insulating film, a layered structure of electrode materials of the second transistor being different from a layered structure of electrode materials of the first transistor; and a first and a second line, the lines being of different potentials, wherein a border between the first and the second region overlaps with at most only the first or the second line.
Public/Granted literature
Information query
Patent Agency Ranking
0/0