Invention Grant
US08742554B2 Circuit member, manufacturing method for circuit members, semiconductor device, and surface lamination structure for circuit member
有权
电路部件，电路部件的制造方法，半导体装置以及电路部件的表面层叠结构
- Patent Title: Circuit member, manufacturing method for circuit members, semiconductor device, and surface lamination structure for circuit member
- Patent Title (中): 电路部件，电路部件的制造方法，半导体装置以及电路部件的表面层叠结构
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Application No.: US11912163Application Date: 2006-04-26
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Publication No.: US08742554B2Publication Date: 2014-06-03
- Inventor: Yo Shimazaki , Hiroyuki Saito , Masachika Masuda , Kenji Matsumura , Masaru Fukuchi , Takao Ikezawa
- Applicant: Yo Shimazaki , Hiroyuki Saito , Masachika Masuda , Kenji Matsumura , Masaru Fukuchi , Takao Ikezawa
- Applicant Address: JP Shinjuku-Ku
- Assignee: Dai Nippon Printing Co., Ltd.
- Current Assignee: Dai Nippon Printing Co., Ltd.
- Current Assignee Address: JP Shinjuku-Ku
- Agency: Burr & Brown, PLLC
- Priority: JP2005-128259 20050426
- International Application: PCT/JP2006/308721 WO 20060426
- International Announcement: WO2006/115267 WO 20061102
- Main IPC: H01L23/495
- IPC: H01L23/495
Abstract:
A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.
Public/Granted literature
Information query
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