A level shift circuit includes a first latch circuit configured to receive a clock signal, a digital data signal, a first supply voltage, and a second supply voltage, and generate a first output signal based on the digital data signal. The first output signal has a first voltage level corresponding to the first supply voltage, and a second voltage level corresponding to the second supply voltage. At least one capacitor is configured to receive the first output signal, and retain a voltage value corresponding to the output signal. A second latch circuit is configured to receive the voltage value, a third supply voltage, and a fourth supply voltage, and generate a second output signal based on the voltage value. The second output signal has a third voltage level corresponding to the third supply voltage and a fourth voltage level corresponding to the fourth supply voltage.