A memory device whose speed at the time of operation such as writing or reading is high and whose number of semiconductor elements per memory cell is small is provided. The memory device includes a control unit, an arithmetic unit, and a buffer memory device. The buffer memory device stores data sent from a main memory device and/or the arithmetic unit, in accordance with an instruction from the control unit. The buffer memory device includes a plurality of memory cells. The memory cells each include a transistor including a channel formation region including an oxide semiconductor, and a memory element to which charge with an amount in accordance with a value of the data is supplied through the transistor. Further, a data retention time of the memory cell corresponding to a valid bit is shorter than a data retention time of the memory cell corresponding to a data field.