Invention Grant
US08743625B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations
有权
半导体集成电路适用于输出内部操作的通过/失败结果
- Patent Title: Semiconductor integrated circuit adapted to output pass/fail results of internal operations
- Patent Title (中): 半导体集成电路适用于输出内部操作的通过/失败结果
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Application No.: US13901093Application Date: 2013-05-23
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Publication No.: US08743625B2Publication Date: 2014-06-03
- Inventor: Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2001-386596 20011219; JP2002-311475 20021025
- Main IPC: G11C7/10
- IPC: G11C7/10
Abstract:
In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
Public/Granted literature
- US20130262754A1 SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULTS OF INTERNAL OPERATIONS Public/Granted day:2013-10-03
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