In memory module populated by memory components having a write-timing calibration mode, control information that specifies a write operation is received via an address/control signal path and write data corresponding to the write operation is received via a data signal path. Each memory component receives multiple delayed versions of a timing signal used to indicate that the write data is valid, and outputs signals corresponding to the multiple delayed versions of the timing signal to enable determination, in a memory controller, of a delay interval between outputting the control information on the address/control signal path and outputting the write data on the data signal path.