Invention Grant
- Patent Title: Multi-stack semiconductor integrated circuit device
- Patent Title (中): 多层半导体集成电路器件
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Application No.: US13501879Application Date: 2010-10-08
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Publication No.: US08744349B2Publication Date: 2014-06-03
- Inventor: Tadahiro Kuroda
- Applicant: Tadahiro Kuroda
- Applicant Address: JP Tokyo
- Assignee: Keio University
- Current Assignee: Keio University
- Current Assignee Address: JP Tokyo
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2009-237872 20091015
- International Application: PCT/JP2010/067727 WO 20101008
- International Announcement: WO2011/046071 WO 20110421
- Main IPC: H04B5/00
- IPC: H04B5/00 ; H04B7/00

Abstract:
The invention relates to a multi-stack semiconductor integrated circuit device where communication between semiconductor chips can be efficiently carried out by bypassing a number of chips. Each semiconductor chip that forms a multi-stack semiconductor integrated circuit device having a stack structure where four or more semiconductor chips having the same shape are stacked on top of each other is provided with: a first coil for transmission/reception for communication between chips over a long distance; and a second coil for transmission/reception for communication between chips over a short distance, of which the size is smaller than that of the above-described first coil for transmission/reception.
Public/Granted literature
- US20120217658A1 MULTI-STACK SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2012-08-30
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