A memory device includes a memory unit, a memory control unit that controls an access of the memory unit, a control unit that performs a communication process with a host device, a data terminal, a reset terminal, and a clock terminal. The control unit outputs a response signal for reporting the connection of the memory device to the host device through the data terminal in an m-th clock cycle (m is at least an integer of 1≦m≦n) corresponding to ID information of the memory device among first to n-th clock cycles (n is an integer of 2 or more) of clocks input to the clock terminal.