Invention Grant
- Patent Title: Memory with segmented error correction codes
- Patent Title (中): 具有分段纠错码的存储器
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Application No.: US13602116Application Date: 2012-09-01
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Publication No.: US08745472B2Publication Date: 2014-06-03
- Inventor: Manish Goel , Dongsuk Jeon
- Applicant: Manish Goel , Dongsuk Jeon
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
A code word is received that was derived from a plurality of smaller code words that represent a data word of 2m data bits and a plurality of error correction code bits. The code word is converted into the plurality of smaller code words and syndromes are computed by multiplying each of the plurality of smaller code words by a check matrix. The syndrome words are processed to determine a number of errors that exist in each of the plurality of smaller code words. A portion of the syndrome words is processed to determine locations of possible errors within the plurality of smaller code words. Up to two errors may be corrected and up to three errors may be detected in the code word by using the number of errors and the locations of possible errors to determine erroneous bits in the code word.
Public/Granted literature
- US20140068391A1 Memory with Segmented Error Correction Codes Public/Granted day:2014-03-06
Information query
IPC分类: