Invention Grant
- Patent Title: Layout method and system for multi-patterning integrated circuits
- Patent Title (中): 多图案集成电路的布局方法和系统
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Application No.: US13535705Application Date: 2012-06-28
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Publication No.: US08745556B2Publication Date: 2014-06-03
- Inventor: Huang-Yu Chen , Tsong-Hua Ou , Ken-Hsien Hsieh , Chin-Hsiung Hsu
- Applicant: Huang-Yu Chen , Tsong-Hua Ou , Ken-Hsien Hsieh , Chin-Hsiung Hsu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Agent Steven E. Koffs
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G03F1/00

Abstract:
A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.
Public/Granted literature
- US20140007026A1 LAYOUT METHOD AND SYSTEM FOR MULTI-PATTERNING INTEGRATED CIRCUITS Public/Granted day:2014-01-02
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