A method includes creating a technology file including data for an integrated circuit including at least one die including at least one metal layer to be formed using at least one of a single patterning process or a multi-patterning process, creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the metal layer of at least one die based on the technology file, simulating a performance of the integrated circuit based on the netlist, adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and repeating the simulating and adjusting to optimize the at least one of the capacitive or inductive couplings.