Invention Grant
US08745560B1 Methods for generating a user interface for timing budget analysis of integrated circuit designs 有权
用于生成用于集成电路设计的时序预算分析的用户界面的方法

Methods for generating a user interface for timing budget analysis of integrated circuit designs
Abstract:
In one embodiment of the invention, a method includes reading an automatically generated timing budgeting file, including timing budget information for a plurality of partitions of an integrated circuit design; graphically displaying a time budgeting debug window on a display device; and graphically displaying a timing budget analyzer window on the display device in response to selection of a selected signal path in a path list window pane. The timing budget analyzer window graphically displays timing budgets and timing delays of a selected path for visual comparison. The time budgeting debug window includes a button with a path category menu to display one or more signal paths meeting a selected path category, and a path list window pane to display a list of one or more signal paths through one or more ports of the plurality of partitions in response to the selected path category in the path category menu.
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