Invention Grant
US08745566B1 Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device
失效
用于利用可编程逻辑器件上的设计路由的约束的方法和装置
- Patent Title: Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device
- Patent Title (中): 用于利用可编程逻辑器件上的设计路由的约束的方法和装置
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Application No.: US13861628Application Date: 2013-04-12
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Publication No.: US08745566B1Publication Date: 2014-06-03
- Inventor: Vaughn Betz , Caroline Pantofaru , Jordan Swartz
- Applicant: Altera Corporation
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agent L. Cho
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A method for designing a system on a programmable logic device (PLD) is disclosed. Routing resources are selected for a user specified signal on the PLD in response to user specified routing constraints. Routing resources are selected for a non-user specified signal on the PLD without utilizing the user specified routing constraints.
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