Invention Grant
US08745568B2 Method and apparatus for determining relevance values for a detection of a fault on a chip and for determining a fault probability of a location on a chip
有权
用于确定用于检测芯片上的故障的相关性值并确定芯片上的位置的故障概率的方法和装置
- Patent Title: Method and apparatus for determining relevance values for a detection of a fault on a chip and for determining a fault probability of a location on a chip
- Patent Title (中): 用于确定用于检测芯片上的故障的相关性值并确定芯片上的位置的故障概率的方法和装置
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Application No.: US12671674Application Date: 2008-12-17
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Publication No.: US08745568B2Publication Date: 2014-06-03
- Inventor: Jochen Rivoir
- Applicant: Jochen Rivoir
- Applicant Address: SG Singapore
- Assignee: Advantest (Singapore) Pte Ltd
- Current Assignee: Advantest (Singapore) Pte Ltd
- Current Assignee Address: SG Singapore
- International Application: PCT/EP2008/010787 WO 20081217
- International Announcement: WO2010/069344 WO 20100624
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method for determining relevance values representing a relevance of a combination of an input node of a first number of input nodes with a measurement node of a second number of measurement nodes for a detection of a fault on a chip applies a third number of tests at the first number of input nodes, measures for each test of the third plurality of tests a signal at each of the second number of measurement nodes to obtain for each measurement node of the second number of measurement nodes a third number of measurement values, and determines the relevance values, wherein each relevance value is calculated based on a correlation between the third number of test input choices defined for the input node of the respective combination and the third number of measurement values associated to the measurement node of the respective combination.
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